Field programmable gate array long line routing network

ABSTRACT

A multi-directional routing repeater has a plurality of buffers, each of the plurality of buffers has an input and an output. The output of each of the plurality of buffers is connected to a separate routing line for transmitting a signal in a separate direction of a first set of routing lines, and the input of each of the plurality of buffers is connected to one of a first set of programmable switches, one of a second set of programmable switches, one of a third set of programmable switches, and one of a fourth set of programmable switches, and each one of the first set of programmable switches is connected to a separate one of the second set of programmable switches and a separate one of the second set of programmable switches, none of which are connected to an input of a same one of the plurality of buffers. Each one of the first set of programmable switches is connected to a separate routing line for transmitting a signal in a separate direction of a second set of routing lines.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of co-pending U.S. patent applicationSer. No. 11/692,717, filed Mar. 28, 2007, which is a continuation ofU.S. patent application Ser. No. 11/028,471, filed Dec. 31, 2004, nowissued as U.S. Pat. No. 7,212,030, the entirety of which are herebyincorporated by reference in it's entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a routing network in a fieldprogrammable gate array (FPGA) architecture. More particularly, thepresent invention relates to a long line routing network employingunidirectional buffers for driving signals onto sets of parallel longrouting lines.

2. The Background Art

Programmable logic devices (PLDs) are integrated circuit devices whichcontain gates or other general-purpose cells whose interconnections canbe configured by programming to implement nearly any desiredcombinatorial or sequential function. Field programmable gate arrays(FPGAs) are well known in the PLD art. FPGAs generally include an arrayof general-purpose logic circuits, typically referred to as logicblocks, which can be programmed by programmable elements to implementvirtually any logic function. The programmed logic elements in the gatearray are connected together by routing resources to form a desiredintegrated circuit. The routing resources are connected to each otherand to the logic elements in the gate array by programmable elements.

It is well known in the art that both volatile and non-volatileprogrammable elements have been used to provide interconnection in FPGAdevices. Volatile programmable elements are often a pass transistorcontrolled by a static random access memory (SRAM) cell. Nonvolatileprogrammable elements include antifuses and floating gate transistors.Programmable antifuse based architectures and reprogrammable SRAM andfloating gate memory cell based architectures as well known in the FPGAart.

In an SRAM based reprogrammable FPGA, the programmable elements aretypically passgates controlled by information stored in an SRAMconfiguration memory. In an antifuse based FPGA, the antifuses areprogrammable elements that are formed by two conductors with adielectric material sandwiched in between which represent an open stateuntil programmed. The antifuses are disposed to provide theinterconnections among the routing resources and to program theprogrammable logic elements. In a floating gate transistor based FPGA,the floating gates are typically similar to those used in flash memoriesthe operation of which is well known to those of ordinary skill in theart, but adapted for use in programmable arrays.

A variety of schemes well known to those of ordinary skill in the artfor the implementation of the routing network in an FPGA have beenproposed in the art. These routing schemes have attempted to address anumber of different issues including: reducing the effect of resistancein the routing lines on signal transmission in the circuit; reducing theeffect of capacitance between the routing lines on signal transmissionin the circuit; increasing the reliability of place and route circuitimplementations; and determining the number and lengths of routing linesneeded to efficiently utilize the number and granularity of availablelogic blocks. Granularity is understood by one of ordinary skill in theart to describe the number of inputs into a logic cell, and thereby thecomplexity of the logic expressions that may be implemented by the logiccell.

In Freeman et al., U.S. Pat. No. 5,594,363, a non-volatilereprogrammable based FPGA is disclosed which discusses the lengths andinterconnection of various routing resources, depicted as local, longand global, and the granularity of the logic blocks. The long routingresources are channels that are bidirectional, and the signals on thechannels are driven by buffers as the channels transmit the signals. Aspointed out in Freeman, et al., the number of active programmableconnections on a long routing line is of concern, because they require anot insignificant amount of die area, and also add to the load andcapacitance on the line.

In FIG. 1, a schematic example of a known prior art bidirectionalrouting connection employed in a horizontal long line routing net 10 isillustrated. In the long line routing net 10, first and secondhorizontal routing nets 12 and 14 are each shown having a routing line,16 and 18, respectively, being connected to the bidirectional routingconnection and a vertical routing net 20 having a routing line 22, thatmay be connected to the routing line 18 from the second horizontalrouting net 14 by a programmable switch 24. In the bidirectional routingconnection, the long lines 16 and 18 may be programmably connected tothe input and the output of a buffer 26 by programmable switches 28, 30,32 and 34. The input of buffer 26 may also be programmably connected toground by programmable switch 36.

In the operation of the bidirectional routing connection depicted inFIG. 1, signals from first horizontal routing net 12 are transmitted tosecond horizontal routing net 14 when programmable switches 28 and 32are programmed to conduct, and signals from second horizontal routingnet 14 are transmitted to first horizontal routing net 12 whenprogrammable switches 30 and 34 are programmed to conduct. Signals maybe transmitted between the vertical routing net 20 and the secondhorizontal routing net 14 when programmable switch 24 is programmed toconduct. In the event the buffer 26 is not to be used, programmableswitch 24 is programmed to conduct. In the event the buffer 26 is not tobe used, programmable switch 36 may be employed to pull the input of thebuffer 26 to ground. Although not depicted in FIG. 1, a similarbidirectional routing connection is also known to be employed in thevertical direction for vertical long line resources. Active routingrepeaters are typically used in longer routing resources, where thedistance from on bidirectional routing connection to the nextbidirectional routing connection is typically 4 or 8 tiles or evenlonger.

The bidirectionality of the routing connection is provided by theprogrammable switches 30 and 32 at the output of the buffer 26 as wellas the programmable switches 28 and 34 at the input of the buffer 26.These programmable switches add both serial resistance and switchcapacitance to the routing nets. When a very long net is beingimplemented there can be significant performance degradation resultingfrom the resistance of the switches 30 and 32 at the output of thebuffer 26 due to the increased capacitance imposed by a very long net.Even though the programmable switches 30 and 32 may be implemented asseveral parallel switches to reduce the serial resistance, the parallelswitches add more capacitance and require more die area. Accordingly, itwould be advantageous to implement very long line routing nets withbuffering as desired while reducing the resistance and capacitanceassociated with providing connectability between the long line routingnets.

BRIEF DESCRIPTION OF THE INVENTION

According to a first embodiment of the present invention, amulti-directional routing repeater has a plurality of buffers, each ofthe plurality of buffers has an input and an output. The output of eachof the plurality of buffers is connected to a separate routing line fortransmitting a signal in a separate direction of a first set of routinglines, and the input of each of the plurality of buffers is connected toone of a first set of programmable switches, one of a second setprogrammable switches, one of a third set of programmable switches, andone of a fourth set of programmable switches, and each one of the firstset of programmable switches is connected to a separate one of thesecond set of programmable switches and a separate one of the second setof programmable switches, none of which are connected to an input of asame one of the plurality of buffers. Each one of the first set ofprogrammable switches is connected to a separate routing line fortransmitting a signal in a separate direction of a second set of routinglines.

According to a second embodiment of the present invention, a fieldprogrammable gate array long line bus architecture has a plurality ofmulti-directional routing repeaters, and each of the plurality ofmulti-directional routing repeaters is disposed at a separate tileboundary for each tile in the field programmable gate array. A pluralityof pairs of unidirectional routing lines of uniform length, each of theplurality of pairs has a first routing lines in each of the pairs fortransmitting a signal in a first direction and a second routing line ineach of the pairs for transmitting a signal in a second direction, andeach of the plurality of pairs of unidirectional routing lines begins ata separate one of the plurality of multi-directional routing repeaters.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates schematically a bidirectional routing connection forlong line routing nets according to the prior art.

FIG. 2 illustrates schematically a set of four of unidirectional routingrepeaters for connecting parallel sets of long line routing netsaccording to the present invention.

FIG. 3 illustrates schematically an arrangement of the long routinglines in a bus architecture according to the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

Those of ordinary skill in the art will realize that the followingdescription of the present invention is illustrative only and not in anyway limiting. Other embodiments of the invention will readily suggestthemselves to such skilled persons.

Generally, in a reprogrammable FPGA architecture suitable forincorporating the present invention, there is included an array ofprogrammable logic blocks, routing resources for connecting theprogrammable logic blocks together, an array of routing switch memorycells whose contents are employed to connect the routing resourcestogether, and static configuration memory cells for programming thelogic devices. The logic blocks are often grouped into a unit referredto as a tile. In different FPGA architectures, the tiles may be ofvarious sizes depending on a variety of factors. Typically, however, atile is recognized as a block containing one logic block as well as therouting resources, including programmable switches and partial nets thatare disposed in the vicinity of the logic block. For interconnectionbetween tiles, interconnect resources of various lengths are oftenemployed. Any interconnect resource that runs for a distance greaterthan one tile may be referred to as a long line, but typically a longline will run for a distance that is greater than the minimum distanceof more than one tile.

In FIG. 2, a multi-directional routing repeater including first, second,third, and fourth unidirectional routing repeaters 100-1, 100-2, 100-3and 100-4 for programmably connecting parallel sets of long routinglines according to the present invention is illustrated. Also depictedare horizontal long line routing net 102 and vertical long line routingnet 104. It will be appreciated by those of ordinary skill in the artthat the terms horizontal and vertical are employed to enhance thereadability of the application and should be generally understood toindicate first and second orientations.

Both the horizontal long line routing net 102 and the vertical long linerouting net 104 have pairs of long lines such that one of the long linesin each pair transmit a signal in a first direction and a second one inthe pair transmits a signal in a second direction. The horizontal longline routing net 102 includes a first pair of horizontal long routinglines 106-1 and 106-2 and a second pair of horizontal long routing lines108-1 and 108-2+. The vertical long line routing net 104 includes afirst pair of vertical long routing lines 110-1 and 110-2 and a secondpair of vertical long routing lines 112-1 and 112-2.

First unidirectional routing repeater 100-1 has a buffer 114-1,programmable grounding switch 116-1, programmably horizontal switch118-1, and first and second programmable vertical-to-horizontal switches120-1 and 122-1. A programmable switch 124-1 for connection anillustrative separate routing net 126-1 may also, according to anotheraspect of the present invention, be included in the first unidirectionalrouting repeater 100-1. A first terminal of each of programmablegrounding switch 116-1, programmable horizontal switch 118-1, first andsecond programmable vertical-to-horizontal switches 120-1 and 122-1, andprogrammable switch 124-1 are connected to the input of buffer 114-1.

Second unidirectional routing repeater 100-2 has a buffer 114-2,programmable grounding switch 116-2, programmable horizontal switch118-2, and first and second programmable vertical-to-horizontal switches120-2 and 122-2. A programmable switch 124-2 for connecting anillustrative separate routing net 126-2 may also, according to anotheraspect of the present invention, be included in the secondunidirectional routing repeater 100-2. A first terminal of each ofprogrammable grounding switch 116-2, programmable horizontal switch118-2, first and second programmable vertical-to-horizontal switches120-2 and 122-2, and programmable switch 124-2 are connected to theinput of buffer 114-2.

Third unidirectional routing repeater 100-3 has a buffer 114-3,programmable grounding switch 116-3, programmable vertical switch 118-3,and first and second programmable horizontal-to-vertical switches 120-3and 122-3. A programmable switch 124-3 for connecting an illustrativeseparate routing net 126-3 may also, according to another aspect of thepresent invention, be included in the third unidirectional routingrepeater 100-3. A first terminal of each of programmable groundingswitch 116-3, programmable vertical switch 118-3, first and secondprogrammable horizontal-to-vertical switches 120-3 and 122-3, andprogrammable switch 124-3 are connected to the input of buffer 114-3.

Fourth unidirectional routing repeater 100-4 has a buffer 114-4,programmable grounding switch 116-4, programmable vertical switch 118-4,and first and second programmable horizontal-to-vertical switches 120-4and 122-4. A programmable switch 124-4 for connecting an illustrativeseparate routing net 126-4 may also, according to another aspect of thepresent invention, be included in the fourth unidirectional routingrepeater 100-4. A first terminal of each of programmable groundingswitch 116-4, programmable vertical switch 118-4, first and secondprogrammable horizontal-to-vertical switches 120-4 and 122-4, andprogrammable switch 124-4 are connected to the input of buffer 114-4.

According to the present invention, it should be appreciated that thereare no switches at the outputs of buffers 114-1 through 114-4. This isin contrast to the prior art as illustrated by the output switches 30and 32 seen with reference to FIG. 1. This removes any serial resistanceimposed by switches 30 and 32, as well as their capacitance.

The horizontal long routing line 106-1 is connected to a second terminalof programmable horizontal switch 118-1, a second terminal of secondprogrammable horizontal-to-vertical switch 122-3, and a second terminalof first programmable horizontal-to-vertical switch 120-4. A secondterminal of programmable grounding switch 116-1 is connected to ground,and a second terminal of programmable grounding switch 124-1 isconnected to the separate routing net 126-1. It will be appreciated bythose of ordinary skill in the art that routing net 126-1 isillustrative of any number of routing lines of routing nets of differentrouting networks that could be connected to the input of buffer 114-1 byprogrammable switches in a manner similar to the connection byprogrammable switch 124-1. The horizontal long routing line 106-2 isconnected to the output of buffer 114-2.

The horizontal long routing line 108-1 is connected to a second terminalof programmable horizontal switch 118-2, a second terminal of secondprogrammable horizontal-to-vertical switch 122-4, and a second terminalof first programmable horizontal-to-vertical switch 120-3. A secondterminal of programmable grounding switch 116-2 is connected to ground,and a second terminal of programmable switch 124-2 is connected to theseparate routing net 126-2. It will be appreciated by those of ordinaryskill in the art that routing net 126-2 is illustrative of any number ofrouting lines of routing nets of different routing networks that couldbe connected to the input of buffer 114-2 by programmable switches in amanner similar to the connection by programmable switch 124-2. Thehorizontal long routing line 108-2 is connected to the output of buffer114-1.

The vertical long routing line 110-1 is connected to a second terminalof programmable vertical switch 118-3, a second terminal of secondprogrammable vertical-to-horizontal switch 122-1, and a second terminalof first programmable horizontal-to-vertical switch 120-2. A secondterminal of programmable grounding switch 116-3 is connected to ground,and a second terminal of programmable switch 124-3 is connected to theseparate routing net 126-3. It will be appreciated by those of ordinaryskill in the art that routing net 126-3 is illustrative of any number ofrouting lines of routing nets of different routing networks that couldbe connected to the input of buffer 114-3 by programmable switches in amanner similar to the connection by programmable switch 124-3. Thevertical long routing line 110-2 is connected to the output of buffer114-4.

The vertical long routing line 112-1 is connected to a second terminalof programmable vertical switch 118-4, a second terminal of secondprogrammable vertical-to-horizontal switch 122-2, and a second terminalof first programmable horizontal-to-vertical switch 120-1. A secondterminal of programmable grounding switch 116-4 is connected to ground,and a second of programmable switch 124-4 is connected to the separaterouting net 126-4 is illustrative of any number of routing lines ofrouting nets of different routing networks that could be connected tothe input of buffer 114-4 by programmable switches in a manner similarto the connection by programmable switch 124-4. The vertical longrouting line 112-2 is connected to the output of buffer 114-3.

According to the present invention, programmable switches 116 through124 preferably include non-volatile transistors. It should beappreciated that a variety of non-volatile memory devices well known tothose of ordinary skill in the art may be employed according to thepresent invention including floating gate devices such as EEPROM, flashEEPROM, silicon nanocrystal MOS transistors, and floating trap devicessuch as SONOS and MONOS. To avoid overcomplicating the disclosure andthereby obscuring the present invention descriptions of the abovementioned non-volatile memory devices are not made herein. It should befurther appreciated that other known switching devices such as SRAMcontrolled pass gates and antifuses may be suitable according to thepresent invention.

In the operation of unidirectional routing repeater 100-1, the buffer114-1 can drive a signal from horizontal routing line 106-1 whenprogrammable horizontal switch 118-1 is turned on, from vertical line110-1 when second programmable vertical-to-horizontal switch 122-1 isturned on, from vertical line 112-1 when first programmablevertical-to-horizontal switch 122-1 is turned on, from vertical line112-1 when first programmable vertical-to-horizontal switch 120-1 isturned on, or from an alternative routing net 126-1 when programmableswitch 124-1 is turned on. Otherwise, the buffer 114-1 can be tied toground when programmable grounding switch 116-1 is turned on.

In the operation of unidirectional routing repeater 100-2, the buffer114-2 can drive a signal from horizontal routing line 108-1 whenprogrammable horizontal switch 1418-2 is turned on, from vertical line110-1 when first programmable vertical-to-horizontal switch 120-2 isturned on, from vertical line 112-1 when second programmablevertical-to-horizontal switch 122-2 is turned on, or from an alternativerouting net 126-2 when programmable switch 124-2 is turned on.Otherwise, the buffer 114-2 can be tied to ground when programmablegrounding switch 116-2 is turned on.

In the operation of unidirectional routing repeater 100-3, the buffer114-3 can drive a signal from vertical routing line 110-1 whenprogrammable vertical switch 118-3 is turned on, from horizontal routingline 106-1 when second programmable horizontal-to-vertical switch 122-3is turned on, from horizontal routing line 108-1 when first programmablehorizontal-to-vertical switch 120-3 is turned on, or from an alternativerouting net 126-3 when programmable switch 124-3 is turned on.Otherwise, the buffer 114-3 can be tied to ground when programmablegrounding switch 116-3 is turned on.

In the operation of unidirectional routing repeater 100-4, the buffer114-4 can drive a signal from vertical routing line 112-1 whenprogrammable vertical switch 118-4 is turned on, from horizontal routingline 106-1 when first programmable horizontal-to-vertical switch 120-4is turned on, from horizontal routing line 108-1 when secondprogrammable horizontal-to-vertical switch 122-4 is turned on, or froman alternative routing net 126-4 when programmable switch 124-4 isturned on. Otherwise, the buffer 114-4 can be tied to ground whenprogrammable grounding switch 116-4 is turned on.

It should be further appreciated that the unidirectional routingrepeaters 100-1 through 100-4 may individually and independently selectthe nets from which signals are transmitted to the routing lines 106-2,108-2, 110-2 and 112-2. Accordingly, the same signal may be transmittedto more than one of the routing lines 106-2, 108-2, 110-2 and 112-2. Forexample, by turning on first programmable vertical-to-horizontal switch120-2 and second programmable vertical-to-horizontal switch 122-1simultaneously, a signal on vertical routing line 110-1 would be routedthrough buffers 114-1 and 114-2 simultaneously to the right and to theleft in horizontal direction onto lines 108-2 and 106-2, respectively.In another example, by turning on programmable horizontal switches 118-1and 118-2 simultaneously, a first signal is buffered in a firsthorizontal direction from 106-1 onto 108-2, while a second signal isbuffered in a second horizontal direction from 108-1 to 106-2.

In FIG. 3, a schematic diagram of logic tiles 200 in an FPGA and thearrangement of the horizontal long routing lines in a bus architecturein relation to the logic tiles according to the present invention areillustrated. In the bus architecture, horizontal long routing lines 202for sending signals in a first direction and horizontal long routinglines 204 for sending signals in a second direction are illustrated. Tomost readily illustrate the present invention by avoiding an overlycomplicated drawing figure, only the buffers 114-1 and 114-2 and thehorizontal routing net pairs corresponding to drawing FIG. 2 aredepicted in FIG. 3, and the vertical routing nets and buffers are notdepicted.

In the preferred embodiment, the horizontal long routing lines 202 and204 in the bus architecture are all of the same length. However, theindividual horizontal long routing lines 202 and 204 in the busarchitecture do not start from the same place on the die. The individualhorizontal long routing lines 202 and 204 are staggered so that eachlogic tile 200 in the FPGA logic layout, as described above and asunderstood by those of ordinary skill in the art, has one associatedlong horizontal routing line 202 in first direction and one associatedlong horizontal routing line in a second direction 204. For the logictile 200-1, the set of parallel horizontal long lines having differentdirectionality are indicated as 202-1 and 204-1.

Each individual routing net has a length equal to the tile distancebetween the driving repeater and receiving repeater, whereby in eachtile, the position of the nets within a bus of N nets having N ordinalpositions is changing by +2 or −2 ordinal positions, except theoutermost and innermost ordinal positions, the 1^(st) and Nth ordinalpositions, respectively, from where it changes by +1 or −1 positions.This rotation scheme ensures that an individual line will have twoneighboring lines which are different in any tile position. This reducesany capacitive cross-talk problems. Cross-talk problems are known tohappen when a long line has other long lines as direct neighbors overlong distances, so that the individual capacitance between twoneighboring nets may be a significant portion of its total netcapacitance. A simultaneously switching signal on the neighboring linecould slow down or even create glitches on a signal, which are know ascross-talk problems. The reshuffle pattern of the present inventionmakes sure that the total capacitance of an individual line is composedby a large number of small capacitances, each of them to a differentnet.

For the non-volatile memory cells described above as suitable for useaccording to the present invention, circuits for applying appropriateerase, programming and operating potentials to the floating gate devicesand MOS transistors are well known to those of ordinary skill in the artand are therefore not described herein to avoid overcomplicating thedisclosure and thereby obscuring the present invention.

While the invention has been described with reference to an exemplaryembodiment, it will be understood by those skilled in the art thatvarious changes may be made and equivalents may be substituted forelements thereof without departing from the scope of the invention. Inaddition, many modifications may be made to adapt a particular situationor material to the teachings without departing from the essential scopethereof. Therefore, it is intended that the invention not be limited tothe particular embodiment disclosed as the best mode contemplated forcarrying out this invention, but that the invention will include allembodiments falling within the scope of the appended claims.

1. A unidirectional routing repeater comprising: a buffer having aninput and an output, said output connected to a first routing line fortransmitting a signal in a first direction, a first programmable switchconnected to said input, a second programmable switch connected to saidinput, a third programmable switch connected to said input; and a fourthprogrammable switch connected to said input.